sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 1 post office box 655303 ? dallas, texas 75265 members of the texas instruments widebus ? family d-type flip-flops with qualified storage enable translate between gtl/gtl+ signal levels and lvttl logic levels support mixed-mode signal operation on all ports (5-v input/output voltages with 3.3-v v cc ) i off supports partial-power-down-mode operation bus hold on data inputs eliminates the need for external pullup/pulldown resistors on a port distributed v cc and gnd-pin configuration minimizes high-speed switching noise esd protection exceeds jesd 22 2000-v human-body model (a114-a) 200-v machine model (a115-a) 1000-v charged-device model (c101) latch-up performance exceeds 250 ma per jesd 17 package options include plastic thin shrink small-outline (dgg) and ceramic quad flat (hv) packages description the 'gtl16923 devices are 18-bit registered bus transceivers that provide lvttl-to-gtl/gtl+ and gtl/gtl+-to-lvttl signal-level translation. they are partitioned as two 9-bit transceivers with individual output-enable controls and contain d-type flip-flops for temporary storage of data flowing in either direction. the devices provide an interface between cards operating at lvttl logic levels and a backplane operating at gtl/gtl+ signal levels. higher-speed operation is a direct result of the reduced output swing ( < 1 v), reduced input threshold levels, and output edge control (oec ? ). the user has the flexibility of using these devices at either gtl (v tt = 1.2 v and v ref = 0.8 v) or the preferred higher noise margin gtl+ (v tt = 1.5 v and v ref = 1 v) signal levels. gtl+ is the texas instruments derivative of the gunning transceiver logic (gtl) jedec standard jesd 8-3. the b port normally operates at gtl or gtl+ signal levels, while the a-port and control inputs are compatible with lvttl logic levels. all inputs can be driven from either 3.3-v or 5-v devices which allows use in a mixed 3.3-v/5-v system environment. v ref is the reference input voltage for the b port. data flow in each direction is controlled by the output-enable (oeab and oeba ) and clock (clkab and clkba) inputs. the clock-enable (ceab and ceba ) inputs are used to enable or disable the clock for all 18 bits at a time. however, oeab and oeba are designed to control each 9-bit transceiver independently, which makes the device more versatile. for a-to-b data flow, the device operates on the low-to-high transition of clkab if ceab is low. when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. data flow for b to a is similar to that of a to b but uses oeba , clkba, and ceba . these devices are fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. active bus-hold circuitry holds unused or undriven lvttl inputs at a valid logic state. use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the sn54gtl16923 is characterized for operation over the full military temperature range of 55 c to 125 c. the sn74gtl16923 is characterized for operation from 40 c to 85 c. copyright ? 1999, texas instruments incorporated unless otherwise noted this document contains production data information current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus and oec are trademarks of texas instruments incorporated.
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 2 post office box 655303 ? dallas, texas 75265 sn74gtl16923 . . . dgg package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ceab 1a1 gnd 1a2 1a3 gnd v cc 1a4 gnd 1a5 1a6 gnd 1a7 1a8 gnd 1a9 2a1 gnd 2a2 2a3 gnd 2a4 2a5 gnd 2a6 v cc gnd 2a7 2a8 gnd 2a9 ceba clkab 1oeab 1oeba 1b1 gnd 1b2 1b3 v cc 1b4 1b5 1b6 gnd 1b7 1b8 gnd 1b9 2b1 gnd 2b2 2b3 gnd 2b4 2b5 2b6 v ref 2b7 2b8 gnd 2b9 2oeba 2oeab clkba 1b4 1b5 1b6 gnd 1b7 1b8 gnd 1b9 nc 2b1 gnd 1a4 gnd 1a3 1a2 gnd nc gnd 1b2 2b2 2b3 gnd 2b4 2b5 2b6 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9876543216867666564636261 gnd 1a5 1a6 gnd 1a7 1a8 gnd 1a9 nc 2a1 gnd 2a2 2a3 gnd 2a4 2a5 gnd gnd 2a7 2a8 gnd 2a9 clkba 2b9 gnd 2b8 2b7 v cc v ref sn54gtl16923 . . . hv package (top view) v cc ceab clkab 1oeab 1oeba 1a1 1b1 1b3 v cc 2a6 ceba nc 2oeab 2oeba nc no internal connection 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 function table 2 inputs output mode ceab oeab clkab a b mode x h x x z isolation h l x x b 0 3 latched storage of a data x l h or l x b 0 3 latched storage of a data l l l l clocked storage of a data l l h h clocked storage of a data 2 a-to-b data flow is shown. b-to-a data flow is similar, but uses oeba , clkba, and ceba . 3 output level before the indicated steady-state input conditions were established
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1d clk 1d clk 1b1 1oeab ceab clkab clkba ceba 1oeba 1a1 ce ce 63 1d clk 1d clk 2b1 2oeab 2oeba 2a1 ce ce to eight other channels to eight other channels 1 64 33 32 62 2 34 35 17 61 48 pin numbers shown are for the dgg package. v ref 40
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high or power-off state, v o (see note 1) 0.5 v to 7 v . . . . . . . . . current into any output in the low state, i o : a port 48 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b port 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current into any a-port output in the high state, i o (see note 2) 48 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through each v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 3) 55 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. this current flows only when the output is in the high state and v o > v cc . 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions (see notes 4 through 6) sn54gtl16923 sn74gtl16923 unit min nom max min nom max unit v cc supply voltage 3.15 3.3 3.45 3.15 3.3 3.45 v v tt termination gtl 1.14 1.2 1.26 1.14 1.2 1.26 v v tt voltage gtl+ 1.35 1.5 1.65 1.35 1.5 1.65 v v ref su pp ly voltage gtl 0.74 0.8 0.87 0.74 0.8 0.87 v v ref s u ppl y v oltage gtl+ 0.87 1 1.1 0.87 1 1.1 v v i in p ut voltage b port 0 v tt 0 v tt v v i inp u t v oltage except b port 0 5.5 0 5.5 v v ih high-level b port v ref +50 mv v ref +50 mv v v ih g input voltage except b port 2 2 v v il low-level b port v ref 50 mv v ref 50 mv v v il input voltage except b port 0.8 0.8 v i ik input clamp current 18 18 ma i oh high-level output current a port 24 24 ma i ol low-level a port 24 24 ma i ol output current b port 50 50 ma t a operating free-air temperature 55 125 40 85 c notes: 4. all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report implications of slow or floating cmos inputs , literature number scba004. 5. normal connection sequence is gnd first, v cc = 3.3 v, i/o, control inputs, v tt , v ref (any order) last. 6. v tt and r tt can be adjusted to accommodate backplane impedances as long as they do not exceed the dc absolute i ol ratings. similarly, v ref can be adjusted to optimize noise margins, but normally is 2/3 v tt . product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range for gtl/gtl+ (unless otherwise noted) parameter test conditions sn54gtl16923 sn74gtl16923 unit parameter test conditions min typ 2 max min typ 2 max unit v ik v cc = 3.15 v, i i = 18 ma 1.2 1.2 v v cc = 3.15 v to 3.45 v, i oh = 100 m a v cc 0.2 v cc 0.2 v oh a port v cc = 3 15 v i oh = 12 ma 2.4 2.4 v v cc = 3 . 15 v i oh = 24 ma 2 2 v cc = 3.15 v to 3.45 v, i ol = 100 m a 0.2 0.2 a port v cc = 3 15 v i ol = 12 ma 0.4 0.4 v cc = 3 . 15 v i ol = 24 ma 0.5 0.5 v ol v cc = 3.15 v to 3.45 v, i ol = 100 m a 0.2 0.2 v b p ort i ol = 10 ma 0.2 0.2 b port v cc = 3.15 v i ol = 40 ma 0.4 0.4 i ol = 50 ma 0.55 0.55 b port v cc = 3.45 v v i = 5.5 v or gnd 5 5 i i a-port and control v cc = 3 45 v v i = v cc or gnd 5 5 m a inputs v cc = 3 . 45 v v i = 5.5 v or gnd 20 20 i off v cc = 0, v i or v o = 0 to 5.5 v 100 m a v cc = 3 15 v v i = 0.8 v 75 75 i i(hold) a port v cc = 3 . 15 v v i = 2 v 75 75 m a () v cc = 3.45 v 3 , v i = 0.8 v to 2 v 500 500 i oz a port v cc = 3.45 v, v o = v cc or gnd 10 10 m a i ozh b port v cc = 3.45 v, v o = 1.5 v 10 10 m a v cc = 3.45 v, outputs high 60 60 i cc a or b port v cc = 3 . 45 v , i o = 0, outputs low 60 60 ma v i = v cc or gnd outputs disabled 60 60 d i cc ? v cc = 3.45 v, a-port or control inputs at v cc or gnd, one input at v cc 0.6 v 500 500 m a c i control inputs v i = 3.15 v or 0 2.5 3 2.5 3 pf c i a port v o = 3.15 v or 0 6 8.5 6 8.5 p f c io b port v o = 3.15 v or 0 7 9.5 7 9.5 pf 2 all typical values are at v cc = 3.3 v, t a = 25 c. 3 this is the bus-hold maximum dynamic current. it is the minimum overdrive current required to switch the input from one state t o another. for i/o ports, the parameter i oz includes the input leakage current. ? this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 6 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature for gtl (unless otherwise noted) sn54gtl16923 sn74gtl16923 unit min max min max unit f clock clock frequency 200 200 mhz t w pulse duration, clk high or low 2.5 2.5 ns t setu p time data before clk 2.7 2.6 ns t su set u p time ce before clk 3.5 3.3 ns t h hold time data after clk 0.2 0.1 ns t h hold time ce after clk 0 0 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature for gtl (see figure 1) parameter from to sn54gtl16923 sn74gtl16923 unit parameter (input) (output) min typ 2 max min typ 2 max unit f max 200 200 mhz t plh clkab b 2.1 6 2.2 5.8 ns t phl clkab b 2 6.5 2.1 6.3 ns t dis oeab b 1.6 5.6 1.7 5.3 ns t en oeab b 1.9 5.2 2 5 ns slew rate both transitions 0.5 0.5 v/ns t r transition time, b outputs (0.6 v to 1 v) 0.2 3 0.3 2.9 ns t f transition time, b outputs (1 v to 0.6 v) 0 4.3 0.1 3.9 ns t plh clkba a 1.7 5.3 1.8 5 ns t phl clkba a 1.6 5.1 1.7 4.8 ns t en oeba a 1.2 5.1 1.3 4.8 ns t dis oeba a 1.9 5.1 2 4.8 ns 2 all typical values are at v cc = 3.3 v, t a = 25 c. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 7 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature for gtl+ (unless otherwise noted) sn54gtl16923 sn74gtl16923 unit min max min max unit f clock clock frequency 200 200 mhz t w pulse duration, clk high or low 2.5 2.5 ns t setu p time data before clk 2.4 2.3 ns t su set u p time ce before clk 3.5 3.3 ns t h hold time data after clk 0.2 0.1 ns t h hold time ce after clk 0 0 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature for gtl+ (see figure 1) parameter from to sn54gtl16923 sn74gtl16923 unit parameter (input) (output) min typ 2 max min typ 2 max unit f max 200 200 mhz t plh clkab b 2.1 6.1 2.2 4 5.9 ns t phl clkab b 2 6.3 2.1 4 6.1 ns t plh oeab b 1.8 5.4 1.9 3.4 5.2 ns t phl oeab b 1.6 5.4 1.7 3.1 5.1 ns slew rate both transitions 0.5 0.5 v/ns t r transition time, b outputs (0.6 v to 1.3 v) 0.5 2.7 0.6 1.3 2.6 ns t f transition time, b outputs (1.3 v to 0.6 v) 0.3 3.4 0.4 1.3 3 ns t plh clkba a 1.7 5.4 1.8 3.5 5.1 ns t phl clkba a 1.6 5.2 1.7 3.3 4.9 ns t en oeba a 1.2 5.1 1.3 2.9 4.8 ns t dis oeba a 1.9 5.3 2 3.2 5 ns 2 all typical values are at v cc = 3.3 v, t a = 25 c. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54gtl16923, sn74gtl16923 18-bit lvttl-to-gtl/gtl+ bus transceivers scbs674e august 1996 revised november 1999 8 post office box 655303 ? dallas, texas 75265 parameter measurement information v tt = 1.5 v, v ref = 1 v t h t su from output under test c l = 50 pf (see note a) load circuit for a outputs s1 open gnd 500 w 500 w test t plh /t phl t plz /t pzl t phz /t pzh s1 open 6 v gnd t plh t phl 3 v v ref v ref v oh v ol 3 v t w input 3 v voltage waveforms setup and hold times voltage waveforms propagation delay times (clkab to b port) voltage waveforms pulse duration voltage waveforms enable and disable times (a port) timing input data input a port output input v tt test point c l = 30 pf (see note a) from output under test 25 w load circuit for b outputs voltage waveforms propagation delay times (clkba to a port) data input b port notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. 6 v 1.5 v 1.5 v t plh t phl 3 v v oh v ol input output 1.5 v 1.5 v 1.5 v 1.5 v v tt 1.5 v 1.5 v 1.5 v v ref v ref v oh v ol output control output waveform 1 s1 at 6 v (see note b) output waveform 2 s1 at gnd (see note b) t pzl t pzh t plz t phz v ol + 0.3 v v oh 0.3 v 0 v 3 v 3 v 1.5 v 1.5 v 1.5 v 1.5 v 0 v 0 v 0 v 0 v 0 v 3 v 1.5 v 1.5 v 0 v 0 v figure 1. load circuits and voltage waveforms
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
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